The present invention relates to the fabrication of semiconductor integrated circuits, and more specifically to a structure and method of making a semiconductor integrated circuit which is tolerant of mis-alignment of the metal contact pattern to the gate pattern.
In a semiconductor integrated circuit, a metal contact such as tungsten is used to connect the transistor gate, source/drain, and body to backend wiring. A conventional method for forming a metal contact will be briefly explained.
FIGS. 10 and 11 illustrate stages in conventional fabrication of a semiconductor integrated circuit.
Referring to FIG. 10, a conventional method of forming a metal contact in a semiconductor integrated circuit includes a step of forming a gate stack 950 of a PFET 901 and a gate stack 960 of an NFET 903, on a substrate 900 which includes a silicon substrate 902, a buried oxide (BOX) layer 904 and a semiconductor layer 906. Then oxide spacers 972, 982 are formed on side walls of the gate stacks 950, 960 followed by formation of source drain (S/D) extensions 920, 922, 924, 926 in a semiconductor layer 906. Next, nitride spacers 974, 984 are formed on the oxide spacers 972, 982 respectively. Subsequently, S/D regions 912, 914, 916, 918 are formed. Further, using the nitride side walls 974, 984 as masks, metal silicide regions 932, 934, 936, 938 are formed on the S/D regions 912, 914, 916, 918, respectively. Next, a contact liner 988, commonly Si3N4, is deposited over the substrate 900, followed by deposition of an interlayer dielectric layer (IDL) 990 and planerization. Thereafter, photolithographic and etching techniques are used to pattern the IDL 990, forming contact openings 992, 994, 996, 998 that expose the silicide on the S/D regions as illustrated in FIG. 11. The process typically proceeds by a first anisotropic etch process to form openings in the interlayer dielectric 990 stopping on the contact liner 988, followed by a second anisotropic etch through the contact liner 988, using the silicide 932, 934, 936, 938 as an etching stop.
In the photolithography, the pattern for the contact openings is inevitably slightly mis-aligned to the gate pattern. Thus, at least a portion of a contact opening may be mis-aligned over the side walls 974, 984. However, the etch process designed to etch away the contact liner 988, typically nitride, has no selectivity to the spacer 974, 984, which is also typically nitride. Therefore, at least a part of the spacers 974, 978 may be etched through, exposing the underlying semiconductor layer 906. Since the silicide 932, 934, 936, 938 on the S/D regions 912, 914, 916, 918 are formed by using the side walls 974, 984, as masks, no silicide is deposited beneath the spacers 974, 984 in the semiconductor layer 906. Accordingly, the exposed portion of the substrate may be etched, causing problems such as a short 993, 997 between a metal contact and the substrate, and causing unexpected parasitic capacitance.
Further occasionally the semiconductor layer 906 is exposed between the bottom of the spacers 974, 984 and the edges 931, 933, 935, 937 of the silicide 932, 934, 936, 938 even though the spacers 974, 984 are used as masks in forming silicide 932, 934, 936, 938, increasing the possibility of causing a short between a metal contact and the substrate.
Accordingly, there is a need for a structure and method of forming a metal contact that is tolerant of mis-alignment of the contact pattern to the gate pattern and avoids shorts between the contact and substrate.